E.G.S.PILLAY ENGINEERING COLLEGE, NAGAPATTINAM.
DEPARTMENT OF  ELECTICAL AND ELECTRONICS ENGINEERING
ACADEMIC YEAR 2014-15(ODD SEM) 

EE6301 – DIGITAL LOGIC CIRCUITS

IMPORTANT TWO MARKS

				

UNIT-I
1.Mention the important characteristics of digital IC’s? 
•	Fan out 

•	Power dissipation 

•	Propagation Delay 

•	Noise Margin 

•	Fan In 

•	Operating temperature 

•	Power supply requirements 

2.Define Fan-out? 

Fan out specifies the number of standard loads that the output of the gate can drive With out impairmenSt of its normal operation.

3. Define power dissipation?

Power dissipation is measure of power consumed by the gate when fully driven by all its inputs.

4. What is propagation delay?

Propagation delay is the average transition delay time for the signal to propagate from input to output when the signals change in value. It is expressed in ns.

5. Define noise margin?

It is the maximum noise voltage added to an input signal of a digital circuit that does not cause an undesirable change in the circuit output. It is expressed in volts.

6. Define fan in?

Fan in is the number of inputs connected to the gate without any degradation in the voltage level.

7. What is Operating temperature?

All the gates or semiconductor devices are temperature sensitive in nature. The temperature in which the performance of the IC is effective is called as operating temperature. Operating temperature of the IC vary from 00 C to 700 c.

8. What is High Threshold Logic?

Some digital circuits operate in environments, which produce very high noise signals. For operation in such surroundings there is available a type of DTL gate which possesses a high threshold to noise immunity. This type of gate is called HTL logic or High Threshold Logic.

9. What are the types of TTL logic?

1. Open collector output	2. Totem-Pole Output	3. Tri-state output.

10. What is depletion mode operation MOS?

If the channel is initially doped lightly with p-type impurity a conducting channel exists at zero gate voltage and the device is said to operate in depletion mode.

11. What is enhancement mode operation of MOS?

If the region beneath the gate is left initially uncharged the gate field must induce a channel before current can flow. Thus the gate voltage enhances the channel current and such a device is said to operate in the enhancement mode.

12.Mention the characteristics of MOS transistor? 

1.	The n- channel MOS conducts when its gate- to- source voltage is positive. 

2.	The p- channel MOS conducts when its gate- to- source voltage is negative 

3.	Either type of device is turned of if its gate- to- source voltage is zero. 

13.How schottky transistors are formed and state its use? 

A schottky diode is formed by the combination of metal and semiconductor. The presence of schottky diode between the base and the collector prevents the transistor from going into saturation. The resulting transistor is called as schottky transistor. The use of schottky transistor in TTL decreases the propagation delay without a sacrifice of power dissipation.

14.List the different versions of TTL 

1.	TTL (Std.TTL) 2.LTTL (Low Power TTL) 

3. HTTL (High Speed TTL) 4.STTL (Schottky TTL)

5.	LSTTL (Low power Schottky TTL) 

15.Why totem pole outputs cannot be connected together. 

Totem pole outputs cannot be connected together because such a connection might produce excessive current and may result in damage to the devices.

16.State advantages and disadvantages of TTL Advantages: 

Easily compatible with other ICs Low output impedance 

Disadvantages: 

Wired output capability is possible only with tristate and open collector types Special circuits in Circuit layout and system design are required. 

17.When does the noise margin allow digital circuits to function properly? 

When noise voltages are within the limits of VNA(High State Noise Margin) and VNK for a particular logic family.

18. Mention the classification of saturated bipolar logic families.

The bipolar logic family is classified as follows:
•	RTL- Resistor Transistor Logic 

•	DTL- Diode Transistor logic 

•	I2L- Integrated Injection Logic 

•	TTL- Transistor Transistor Logic 

•	ECL- Emitter Coupled Logic 

UNIT-II

1) What are basic properties of Boolean algebra?

The basic properties of Boolean algebra are commutative property, associative Property and distributive property.

2) State the associative property of Boolean algebra.

The associative property of Boolean algebra states that the OR ing of several variables results in the same regardless of the grouping of the variables. The associative property is stated as follows:

A+ (B+C) = (A+B) +C

3) State the commutative property of Boolean algebra.

The commutative property states that the order in which the variables are OR ed makes no difference. The commutative property is:

A+B=B+A

4) State the distributive property of Boolean algebra.

The distributive property states that AND ing several variables and OR ing the result With a single variable is equivalent to OR ing the single variable with each of the the several Variables and then AND ing the sums. The distributive property is:

A+BC= (A+B) (A+C)

5) State the absorption law of Boolean algebra.

The absorption law of Boolean algebra is given by X+XY=X, X(X+Y) =X.

6) State De Morgan's theorem.

De Morgan suggested two theorems that form important part of Boolean algebra. They are,

1) The complement of a product is equal to the sum of the complements. (AB)' = A' + B'

2) The complement of a sum term is equal to the product of the complements. (A + B)' = A'B'

7) Reduce A (A + B)

A (A + B) = AA + AB

=	A (1 + B) [1 + B = 1] 

=	A. 

8)	Reduce A'B'C' + A'BC' + A'BC 

A'B'C' + A'BC' + A'BC = A'C'(B' + B) + A'B'C

=	A'C' + A'BC [A + A' = 1] 

=	A'(C' + BC) 

IMPORTANT TWO MARKS

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DIGITAL LOGIC CIRCUITS

=	A'(C' + B) [A + A'B = A + B] 

9)	Reduce AB + (AC)' + AB’C (AB + C) 

AB + (AC)' + AB’C (AB + C) = AB + (AC)' + AAB'BC + AB'CC

=	AB + (AC)' + AB'CC [A.A' = 0] 

=	AB + (AC)' + AB'C [A.A = 1] 

=	AB + A' + C' =AB'C [(AB)' = A' + B'] 

=	A' + B + C' + AB'C [A + AB' = A + B] 

=	A' + B'C + B + C' [A + A'B = A + B] 

=	A' + B + C' + B'C =A' + B + C' + B' =A' + C' + 1 

=	1 [A + 1 =1] 

10)	Simplify the following expression Y = (A + B) (A + C’) (B' + C’) 

Y = (A + B) (A + C’) (B' + C’) 

=	(AA' + AC +A'B +BC) (B' + C') [A.A' = 0] 

=	(AC + A'B + BC) (B' + C’) 

=	AB'C + ACC' + A'BB' + A'BC' + BB'C + BCC' 

=	AB'C + A'BC' 

11)	Show that (X + Y' + XY) (X + Y') (X'Y) = 0 

(X + Y' + XY)(X + Y')(X'Y) = (X + Y' + X) (X + Y’) (X' + Y) [A + A'B = A + B]

=	(X + Y’) (X + Y’) (X'Y) [A + A = 1] 

=	(X + Y’) (X'Y) [A.A = 1] 

=	X.X' + Y'.X'.Y 

= 0 [A.A' = 0]

12)	Prove that ABC + ABC' + AB'C + A'BC = AB + AC + BC 

ABC + ABC' + AB'C + A'BC=AB(C + C') + AB'C + A'BC =AB + AB'C + A'BC 

=A(B + B'C) + A'BC =A(B + C) + A'BC =AB + AC + A'BC =B(A + C) + AC =AB + BC + AC 

=AB + AC +BC ...Proved 

13)	Convert the given expression in canonical SOP form Y = AC + AB + BC 

Y = AC + AB + BC 

=AC (B + B’) + AB (C + C’) + (A + A') BC 

=ABC + ABC' + AB'C + AB'C' + ABC + ABC' + ABC =ABC + ABC' +AB'C + AB'C' [A + A =1] 

14)	Define duality property. 

				

Duality property states that every algebraic expression deducible from the postulates Of Boolean algebra remains valid if the operators and identity elements are interchanged. If the dual of an algebraic expression is desired, we simply interchange OR and AND operators and replace 1's by 0's and 0's by 1's.

15) Find the complement of the functions F1 = x'yz' + x'y'z and F2 = x (y'z' + yz). By applying De-Morgan's theorem.

F1' = (x'yz' + x'y'z)' = (x'yz')'(x'y'z)' = (x + y' + z)(x + y +z') F2' = [x (y'z' + yz)]' = x' + (y'z' + yz)'

=	x' + (y'z')'(yz)' 

=	x' + (y + z) (y' + z') 

16)	Simplify the following expression Y = (A + B) (A = C) (B + C) 

=	(A A + A C + A B + B C) (B + C) 

=	(A C + A B + B C) (B + C) 

=	A B C + A C C + A B B + A B C + B B C + B C C 

=	A B C 

17)	What are the methods adopted to reduce Boolean function? 

i)	Karnaug map 

ii)	Tabular method or Quine Mc-Cluskey method 

iii)	Variable entered map technique. 

18)	State the limitations of karnaugh map. 

i)	Generally it is limited to six variable map (i.e) more then six variable involving expression are not reduced. 

ii)	The map method is restricted in its capability since they are useful for simplifying only Boolean expression represented in standard form. 

19)	What is a karnaugh map? 

A karnaugh map or k map is a pictorial form of truth table, in which the map diagram is made up of squares, with each squares representing one minterm of the function.44) Find the minterms of the logical expression

Y = A'B'C' + A'B'C + A'BC + ABC'

Y = A'B'C' + A'B'C + A'BC + ABC' =m0 + m1 +m3 +m6

=_m (0, 1, 3, 6)

20) Write the maxterms corresponding to the logical expression Y = (A + B + C’) (A + B' + C') (A' + B' + C)

=	(A + B + C’) (A + B' + C') (A' + B' + C) 

=M1.M3.M6 

=	M (1, 3, 6) 

21) What are called don’t care conditions?

In some logic circuits certain input conditions never occur, therefore the Corresponding output never appears. In such cases the output level is not defined, it can be either high or low. These output levels are indicated by ‘X’ or‘d’ in the truth tables and are called don’t care conditions or incompletely specified functions.

22) What is a prime implicant?

A prime implicant is a product term obtained by combining the maximum possible number of adjacent squares in the map.

23) What is an essential implicant?

If a min term is covered by only one prime implicant, the prime implicant is said to be essential

24) Define combinational logic

When logic gates are connected together to produce a specified output for certain specified combinations of input variables, with no storage involved, the resulting circuit is called combinational logic.

26)	Explain the design procedure for combinational circuits 

The problem definition 

Determine the number of available input variables & required O/P variables. Assigning letter symbols to I/O variables 

Obtain simplified Boolean expression for each O/P. Obtain the logic diagram. 

27)	Define half adder and full adder 

The logic circuit that performs the addition of two bits is a half adder. The circuit that Performs the addition of three bits is a full adder.

28) Define Decoder?

A decoder is a multiple - input multiple output logic circuit that converts coded inputs into coded outputs where the input and output codes are different.

29) What is binary decoder?

A decoder is a combinational circuit that converts binary information from n input lines to a maximum of 2n out puts lines.

30) Define Encoder?

An encoder has 2n input lines and n output lines. In encoder the output lines generate the binary code corresponding to the input value.

31) What is priority Encoder?

				

A priority encoder is an encoder circuit that includes the priority function. In priority encoder, if 2 or more inputs are equal to 1 at the same time, the input having the highest priority will take precedence.

32) Define multiplexer?

Multiplexer is a digital switch. If allows digital information from several sources to be routed onto a single output line.

33) What do you mean by comparator?

A comparator is a special combinational circuit designed primarily to compare the relative magnitude of two binary numbers.

34) Write down the steps in implementing a Boolean function with levels of NAND Gates?

Simplify the function and express it in sum of products.

Draw a NAND gate for each product term of the expression that has at least two Literals.

The inputs to each NAND gate are the literals of the term. This constitutes a group of first level gates. Draw a single gate using the AND-invert or the invert- OR graphic symbol in the second level, with inputs coming from outputs of first level gates. A term with a single literal requires an inverter in the first level. How ever if the single literal is complemented, it can be connected directly to an input of the second level NAND gate.

35) Give the general procedure for converting a Boolean expression in to multilevel NAND diagram?

Draw the AND-OR diagram of the Boolean expression.

Convert all AND gates to NAND gates with AND-invert graphic symbols. Convert all OR gates to NAND gates with invert-OR graphic symbols. Check all the bubbles in the same diagram. For every bubble that is not

compensated by another circle along the same line, insert an inverter or complement the input

literal.

UNIT-III

1. What are the classifications of sequential circuits?

The sequential circuits are classified on the basis of timing of their signals into two types. They are,

1)	Synchronous sequential circuit. 

2)	Asynchronous sequential circuit. 

2. Define Flip flop.

The basic unit for storage is flip flop. A flip-flop maintains its output state either at 1 or 0 until directed by an input signal to change its state.

3. What are the different types of flip-flop?

There are various types of flip flops. Some of them are mentioned below they are,
•	RS flip-flop 
         SR flip-flop 

•	D flip-flop 

•	JK flip-flop 

•	T flip-flop 

•	
4.	What is the operation of RS flip-flop? 
•	When R input is low and S input is high the Q output of flip-flop is set. 

•	When R input is high and S input is low the Q output of flip-flop is 

reset. 
•	When both the inputs R and S are low the output does not change 

•	When both the inputs R and S are high the output is unpredictable. 
Ø

5. What is the operation of SR flip-flop?

  When R input is low and S input is high the Q output of flip-flop is set.   When R input is high and S input is low the Q output of flip-flop is reset.   When both the inputs R and S are low the output does not change.   Whenboth the inputs R and S are high the output is unpredictable.

6. What is the operation of D flip-flop?

In D flip-flop during the occurrence of clock pulse if D=1, the output Q is set and if D=0, the output is reset.

7. What is the operation of JK flip-flop?

  When K input is low and J input is high the Q output of flip-flop is set.   When K input is high and J input is low the Q output of flip-flop is reset.   When both the inputs K and J are low the output does not change   When both the inputs K and J are high it is possible to set or reset the

Flip-flop (ie) the output toggle on the next positive clock edge.

8. What is the operation of T flip-flop?

T flip-flop is also known as Toggle flip-flop. WhenT=0 there is no change in the output.

  When T=1 the output switch to the complement state (ie) the output toggles.

9. Define race around condition.

In JK flip-flop output is fed back to the input. Therefore change in the output

results change in the input. Due to this in the positive half of the clock pulse if both J and K are high then output toggles continuously. This condition is called race around condition’.

10. What is edge-triggered flip-flop?

The problem of race around condition can solved by edge triggering flip flop. The term edge triggering means that the flip-flop changes state either at the positive edge or negative edge of the clock pulse and it is sensitive to its inputs only at this transition of the clock.

11. What is a master-slave flip-flop?

A master-slave flip-flop consists of two flip-flops where one circuit serves as a master and the other as a slave.

12. Explain the flip-flop excitation tables for RS FF.

In RS flip-flop there are four possible transitions from the present state to the next state. They are,

_ 0_0 transition: This can happen either when R=S=0 or when R=1 and S=0. _ 0_1 transition: This can happen only when S=1 and R=0.

_ 1_0 transition: This can happen only when S=0 and R=1.

_ 1_1 transition: This can happen either when S=1 and R=0 or S=0 and R=0.

13. Explain the flip-flop excitation tables for JK flip-flop

In JK flip-flop also there are four possible transitions from present state to next state.They are,

_ 0_0 transition: This can happen when J=0 and K=1 or K=0.

_ 0_1 transition: This can happen either when J=1 and K=0 or when J=K=1. _ 1_0 transition: This can happen either when J=0 and K=1 or when J=K=1. _ 1_1 transition: This can happen when K=0 and J=0 or J=1.

14. Explain the flip-flop excitation tables for D flip-flop

In D flip-flop the next state is always equal to the D input and it is independent of the present state. Therefore D must be 0 if Qn+1 has to 0, and if Qn+1 has to be 1 regardless the value of Qn.

15. Explain the flip-flop excitation tables for T flip-flop

When input T=1 the state of the flip-flop is complemented; when T=0, the state of the Flip-flop remains unchanged. Therefore, for 0_0 and 1_1 transitions T must be 0 and for 0_1 and 1_0 transitions must be 1.

16. Define sequential circuit?

In sequential circuits the output variables dependent not only on the present input variables but they also depend up on the past history of these input variables.

17.	Give the comparison between combinational circuits and sequential circuits. 

Combinational circuits Sequential circuits Memory unit is not required Memory unity is 

required

Parallel adder is a combinational circuit Serial adder is a sequential circuit

18. What do you mean by present state?

The information stored in the memory elements at any given time define.s the present state of the sequential circuit.

19. What do you mean by next state?

The present state and the external inputs determine the outputs and the next state of the sequential circuit.

20.	State the types of sequential circuits? 

1.	Synchronous sequential circuits 

2.	Asynchronous sequential circuits 

21.	Define synchronous sequential circuit 

In synchronous sequential circuits, signals can affect the memory elements only at discrete instant of time.

22. Define Asynchronous sequential circuit?

In asynchronous sequential circuits change in input signals can affect memory element at any instant of time.

23. Give the comparison between synchronous & Asynchronous sequential circuits?

Synchronous sequential circuits Asynchronous sequential circuits. Memory elements are locked flip-flops Memory elements are either unlocked flip - flops or time delay elements.

24. What is race around condition?

In the JK latch, the output is feedback to the input, and therefore changes in the output results change in the input. Due to this in the positive half of the clock pulse if J and K are both high then output toggles continuously. This condition is known as race around condition

25. Give the comparison between synchronous & Asynchronous counters.

Asynchronous counters	Synchronous counters	
In this type of counter flip-flops are	In this type there is no connection between	
Connected in such a way that output of	output of first flip-flop and clock input of	
1st Flip-flop drives the clock for the next	the next flip – flop	
flipflop		
All the flip-flops are not clocked	All the flip-flops are clocked simultaneously	
Simultaneously		

UNIT-III

1. What are secondary variables?

-present state variables in asynchronous sequential circuits

2. What are excitation variables?

-next state variables in asynchronous sequential circuits

3. What is fundamental mode sequential circuit?

-input variables changes if the circuit is stable -inputs are levels, not pulses

-only one input can change at a given time

4.	What is pulse mode circuit? 

-inputs are pulses 

-widths of pulses are long for circuit to respond to the input 

-pulse width must not be so long that it is still present after the new state is reached 

5.	What are the significance of state assignment? 

•	In synchronous circuits-state assignments are made with the objective of circuit 

reduction
•	Asynchronous circuits-its objective is to avoid critical races 

6.	When does race condition occur? 

-Two or more binary state variables change their value in response to the change in i/p Variable

7. What is non critical race?

Final stable state does not depend on the order in which the state variable changes race condition is not harmful

8. What is critical race?

-final stable state depends on the order in which the state variable changes -race condition is harmful

9. When does a cycle occur?

-asynchronous circuit makes a transition through a series of unstable state

10.	What are the different techniques used in state assignment? 

-shared row state assignment -One hot state assignment 

11.	What are the steps for the design of asynchronous sequential circuit? 

-construction of primitive flow table -reduction of flow table 

-state assignment is made	-realization of primitive flow table

12. What is hazard?

-unwanted switching transients

13. What is static 1 hazard?

-output goes momentarily 0 when it should remain at 1

14. What are static 0 hazards?

-output goes momentarily 1 when it should remain at 0

15. What is dynamic hazard?

-output changes 3 or more times when it changes from 1 to 0 or 0 to 1

16. What is the cause for essential hazards?

-unequal delays along 2 or more path from same input

17. What is flow table?

-state table of an synchronous sequential network

18. What is SM chart?

-describes the behavior of a state machine -used in hardware design of digital systems

19.	What are the advantages of SM chart? 

-easy to understand the operation 

-east to convert to several equivalent forms 

20.	What is primitive flow chart? 

-one stable state per row

21. What is state equivalence theorem?

Two states SA and SB, are equivalent if and only if for every possible input X sequence, the outputs are the same and the next states are equivalent i.e., if SA (t + 1) = SB (t + 1) and ZA = ZB then SA = SB.

22. What do you mean by distinguishing sequences?

Two states, SA and SB of sequential machine are distinguishable if and only if their exists at least one finite input sequence. Which, when applied to sequential machine causes different output sequences depending on whether SA or SB is the initial state.

23. Prove that the equivalence partition is unique

Consider that there are two equivalence partitions exist: PA and PB, and PA) PB. This states that, there exist 2 states Si & Sj which are in the same block of one partition and not in the same block of the other. If Si & Sj are in different blocks of say PB, there exists at least on input sequence which distinguishes Si & Sj and therefore, they cannot be in the same block of PA.

24. Define compatibility.

States Si and Sj said to be compatible states, if and only if for every input sequencethat affects the two states, the same output sequence, occurs whenever both outputs arespecified and regardless of whether Si on Sj is the initial state.

25. Define merger graph.

The merger graph is defined as follows. It contains the same number of vertices as the state table contains states. A line drawn between the two state vertices indicates each compatible state pair. It two states are incompatible no connecting line is drawn.

26. Define incompatibility

The states are said to be incompatible if no line is drawn in between them. If implied states are incompatible, they are crossed & the corresponding line is ignored

.

27.	Explain the procedure for state minimization. 

1.	Partition the states into subsets such that all states in the same subsets are 1 - equivalent. 

2.	Partition the states into subsets such that all states in the same subsets are 2 - equivalent. 

3.	Partition the states into subsets such that all states in the same subsets are 3 - equivalent. 

28.	Define closed covering. 

A Set of compatibles is said to be closed if, for every compatible contained in the set, all its implied compatibles are also contained in the set. A closed set of compatibles, which contains all the states of M, is called a closed covering.

29. Define machine equivalence.

Two machines, M1 and M2 are said to be equivalent if and only if, for every state in M1, there is a corresponding equivalent state in M2 & vice versa.

30. Define state table.

For the design of sequential counters we have to relate present states and next states. The table, which represents the relationship between present states and next states, is called state table.

31. Define total state.

The combination of level signals that appear at the inputs and the outputs of the delays define what is called the total state of the circuit.

32.	What are the steps for the design of asynchronous sequential circuit? 

1.	Construction of a primitive flow table from the problem statement. 

2.	Primitive flow table is reduced by eliminating redundant states using the state Reduction 

3.	State assignment is made 

4.	The primitive flow table is realized using appropriate logic elements. 

33.	Define primitive flow table. 

It is defined as a flow table which has exactly one stable state for each row in the table. The design process begins with the construction of primitive flow table.

34.	What are the types of asynchronous circuits? 

1.	Fundamental mode circuits 

2.	Pulse mode circuits 

35.	Give the comparison between state Assignment Synchronous circuit and state assignment asynchronous circuit. 

In synchronous circuit, the state assignments are made with the objective of circuit reduction. In asynchronous circuits, the objective of state assignment is to avoid critical races. 

				

36. What are races?

When 2 or more binary state variables change their value in response to a change in an input variable, race condition occurs in an asynchronous sequential circuit. In case of unequal delays, a race condition may cause the state variables to change in an unpredictable manner.

37. Define non critical race.

If the final stable state that the circuit reaches does not depend on the order in which the state variable changes, the race condition is not harmful and it is called a non critical race.

38. Define critical race?

If the final stable state depends on the order in which the state variable changes, the race condition is harmful and it is called a critical race.

39. What is a cycle?

A cycle occurs when an asynchronous circuit makes a transition through a series of unstable states. If a cycle does not contain a stable state, the circuit will go from one unstable to stable to another, until the inputs are changed.

40.	List the different techniques used for state assignment. 

1.	Shared row state assignment 

2.	One hot state assignment. 

41.	Write a short note on fundamental mode asynchronous circuit. 

Fundamental mode circuit assumes that. The input variables change only when the circuit is stable. Only one input variable can change at a given time and inputs are levels and not pulses.

42. Write a short note on pulse mode circuit.

Pulse mode circuit assumes that the input variables are pulses instead of level. The width of the pulses is long enough for the circuit to respond to the input and the pulse width must not be so long that it is still present after the new state is reached.

43. Write short note on shared row state assignment.

Races can be avoided by making a proper binary assignment to the state variables. Here, the state variables are assigned with binary numbers in such a way that only one state variable can change at any one state variable can change at any one time when a state transition occurs. To accomplish this, it is necessary that states between which transitions occur be given adjacent assignments. Two binary are said to be adjacent if they differ in only one variable.

44. Write short note on one hot state assignment.

The one hot state assignment is another method for finding a race free stateassignment. In this method, only one variable is active or hot for each row in the original

flow table, ie, it requires one state variable for each row of the flow table. Additional row are introduced to provide single variable changes between internal state transitions.

45)Explain with neat diagram the different hazards and the way to eliminate them. 

Classification of hazards 

Static hazard & Dynamic hazard definitions K map for selected functions 

Method of elimination Essential hazards 

46)State with a neat example the method for the minimization of primitive flow table. 

Consider a state diagram Obtain the flow table 

Using implication table reduce the flow table Using merger graph obtain maximal compatibles Verify closed & covered conditions 

Plot the reduced flow table 

47)Design a asynchronous sequential circuit with 2 inputs T and C. The output attains a value of 1 when T = 1 & c moves from 1 to 0. Otherwise the output is 0. 

Obtain the state diagram Obtain the flow table 

Using implication table reduce the flow table Using merger graph obtain maximal compatibles Verify closed & covered conditions 

Plot the reduced flow table Obtain transition table Excitation table 

Logic diagram 

48. Explain ROM

A read only memory (ROM) is a device that includes both the decoder and the OR gates within a single IC package. It consists of n input lines and m output lines. Each bit Combination of the input variables is called an address. Each bit combination that comes out of the output lines is called a word. The number of distinct addresses possible with n input variables is 2n.

49.What are the types of ROM? 

1.	PROM 

2.	EPROM 

3.	EEPROM 

50.	Explain PROM. 

PROM (Programmable Read Only Memory) it allows user to store data or program. PROMs use the fuses with materiallike nichrome and polycrystalline. The user can blow these fuses by passingaround 20 to 50 mA of current for the period 5 to 20μs.The blowing of fuses is called programming of ROM. The PROMs are one time programmable. Once programmed, the information is stored permanent.

51. Explain EPROM.

EPROM (Erasable Programmable Read Only Memory) EPROM use MOS circuitry. They store 1’s and 0’s as a packet of charge in a buried layer of the IC chip. We can erase the stored data in the EPROMs by exposing the chip to ultraviolet light via its quartz window for 15 to 20 minutes. It is not possible to erase selective information. The chip can be reprogrammed.

52. Explain EEPROM.

EEPROM (Electrically Erasable Programmable Read Only Memory). EEPROM also use MOS circuitry. Data is stored as charge or no charge on an insulated layer or an insulated floating gate in the device. EEPROM allows selective erasing at the register level rather than erasing all the information since the information can be changed by using electrical signals.

53. Define address and word:

In a ROM, each bit combination of the input variable is called on address. Each bit combination that comes out of the output lines is called a word.

54)What are the types of ROM.? 

1.	Masked ROM. 

2.	Programmable Read only Memory 

3.	Erasable Programmable Read only memory. 

4.	Electrically Erasable Programmable Read only Memory. 

56)What is programmable logic array? How it differs from ROM? 

In some cases the number of don’t care conditions is excessive, it is more economical to use a second type of LSI component called a PLA. A PLA is similar to a ROM in concept; however it does not provide full decoding of the variables and does not generates all the minterms as in the ROM.

57) What is mask - programmable?

With a mask programmable PLA, the user must submit a PLA program table to the manufacturer.

58) What is field programmable logic array?

The second type of PLA is called a field programmable logic array. The user by means of certain recommended procedures can program the EPLA.

59)List the major differences between PLA and PAL 

PLA: 

Both AND and OR arrays are programmable and Complex Costlier than PAL PAL 

AND arrays are programmable OR arrays are fixed Cheaper and Simpler 

60)Define PLD. 

Programmable Logic Devices consist of a large array of AND gates and OR gates that Can be programmed to achieve specific logic functions.

61) Give the classification of PLDs.

PLDs are classified as PROM (Programmable Read Only Memory), Programmable Logic Array (PLA), Programmable Array Logic (PAL), and Generic Array Logic (GAL)

62) Define PROM.

PROM is Programmable Read Only Memory. It consists of a set of fixed AND gates Connected to a decoder and a programmable OR array.

63) Define PLA.

PLA is Programmable Logic Array (PLA). The PLA is a PLD that consists of a Programmable AND array and a programmable OR array.

64). Define PAL.

PAL is Programmable Array Logic. PAL consists of a programmable AND array and a fixed OR array with output logic.

65). Why was PAL developed?

It is a PLD that was developed to overcome certain disadvantages of PLA, such as longer delays due to additional fusible links that result from using two programmable arrays and more circuit complexity.

66) Define GAL.

GAL is Generic Array Logic. GAL consists of a programmable AND array and a fixed OR array with output logic.

67) Why the input variables to a PAL are buffered

The input variables to a PAL are buffered to prevent loading by the large number of AND gate inputs to which available or its complement can be connected.

66)What does PAL 10L8 specify? 

PAL - Programmable Logic Array 10 - Ten inputs 

L - Active LOW Ouput 8 - Eight Outputs 

67)What is CPLD? 

CPLDs are Complex Programmable Logic Devices. They are larger versions of PLDs with a centralized internal interconnect matrix used to connect the device macro cells together.

68) Define bit, byte and word.

The smallest unit of binary data is bit. Data are handled in a 8 bit unit called byte. A complete unit of information is called a word which consists of one or more bytes.

69) How many words can a 16x8 memory can store?

A 16x8 memory can store 16,384 words of eight bits each

70) Define address of a memory.

The location of a unit of data in a memory is called address.

71) What is Read and Write operation?

The Write operation stores data into a specified address into the memory and the Read operation takes data out of a specified address in the memory.

72) Why RAMs are called as Volatile?

RAMs are called as Volatile memories because RAMs lose stored data when the power is turned OFF.

73) Define ROM.

ROM is a type of memory in which data are stored permanently or semi permanently. Data can be read from a ROM, but there is no write operation.

74) Define RAM.

RAM is Random Access Memory. It is a random access read/write memory. The data can be read or written into from any selected address in any sequence.

75) Define Static RAM and dynamic RAM.

Static RAM use flip flops as storage elements and therefore store data indefinitely as long as dc power is applied. Dynamic RAMs use capacitors as storage elements and cannot retain data very long without capacitors being recharged by a process called refreshing.

76). List the two types of SRAM.

Asynchronous SRAMs and Synhronous Burst SRAMs

77). List the basic types of DRAMs.

Fast Page Mode DRAM,Extended Data Out DRAM(EDO DRAM),Burst EDO DRAM and Synchronous DRAM.

78) Define a bus.

A bus is a set of conductive paths that serve to interconnect two or more functional components of a system or several diverse systems.

79) Define Cache memory.

It is a relatively small, high-speed memory that can store the most recently used instructions or data from larger but slower main memory.

81). What is the technique adopted by DRAMs.

DRAMs use a technique called address multiplexing to reduce the number of address

lines.

82)Give the feature of UV EPROM.

UV EPROM is electrically programmable by the user, but the store data must be erased by exposure to ultra violet light over a period of several minutes.

83) Give the feature of flash memory.

The ideal memory has high storage capacity, non-volatility; in-system read and write capability, comparatively fast operation. The traditional memory technologies such as ROM, PROM, EEPROM individually exhibits one of these characteristics, but no single technology has all of them except the flash memory.

84) What are Flash memories?

They are high density read/write memories that are non-volatile, which means data can be stored indefinitely with out power.

85)List the three major operations in a flash memory. 

Programming, Read and Erase operation 

86)What is a FIFO memory? 

The term FIFO refers to the basic operation of this type of memory in which the first data bit written into the memory is to first to be read out.

87) List basic types of programmable logic devices.

1. Read only memory	2. Programmable logic Array

3.	Programmable Array Logic 

88)Define address and word. 

In a ROM, each bit combination of the input variable is called on address. Each bit combination that comes out of the output lines is called a word.

89) What is programmable logic array? How it differs from ROM?

In some cases the number of don’t care conditions is excessive, it is more economical to use a second type of LSI component called a PLA. A PLA is similar to a ROM in concept; however it does not provide full decoding of the variables and does not generates all the minterms as in the ROM.

90) What is mask - programmable?

With a mask programmable PLA, the user must submit a PLA PLA program table to the manufacturer.

91) Give the comparison between PROM and PLA.		
	PROM	PLA	
1.	And array is fixed and OR	Both AND and OR arrays are	
array is programmable.	Programmable.	
2.	Cheaper and simple to use.	Costliest and complex than	
PROMS.			

			

UNIT-V VHDL

TWO MARKS

1. What is Verilog?

Verilog is a general purpose hardware descriptor language. It is similar in syntax to the C programming language. It can be used to model a digital system at many levels of abstraction ranging from the algorithmic level to the switch level.

2. What are the various modeling used in Verilog?

1.	Gate-level modeling		2.	Data-flow modeling		
3.	Switch-level modeling	4.	Behavioral modeling		

3. What is the structural gate-level modeling?

Structural modeling describes a digital logic networks in terms of the components that make up the system. Gate-level modeling is based on using primitive logic gates and specifying how they are wired together.

4. What is Switch-level modeling?

Verilog allows switch-level modeling that is based on the behavior of MOSFETs. Digital circuits at the MOS-transistor level are described using the MOSFET switches.

5. What are identifiers?

Identifiers are names of modules, variables and other objects that we can reference in the design. Identifiers consists of upper and lower case letters, digits 0 through 9, the underscore character(_) and the dollar sign($). It must be a single group of characters. Examples: A014, a, b, in_o, s_out

6. What are the value sets in Verilog?

Verilog supports four levels for the values needed to describe hardware referred to as value sets.

Value levels	Condition in hardware circuits

0	Logic zero, false condition

1	Logic one, true condition

X	Unknown logic value

Z	High impedance, floating state

7. What are the types of gate arrays in ASIC?

1) Channeled gate arrays	2) Channel less gate arrays   3) Structured gate arrays

8. Give the classifications of timing control

Methods of timing control:

1.	Delay-based timing control 

2.	Event-based timing control 

3.	Level-sensitive timing control Types of delay-based timing control: 

1.	Regular delay control 

2.	Intra-assignment delay control 

3.	Zero delay control 

Types of event-based timing control: 

1.	Regular event control 

2.	Named event control 

3.	Event OR control 

4.	Level-sensitive timing control 

			
	DIGITAL LOGIC CIRCUITS		
9 .Give the different arithmetic operators?		
Operator symbol	Operation performed	Number of	
operands			
*	Multiply	Two	
/	Divide	Two	
+	Add	Two	
-	Subtract	Two	
%	Modulus	Two	
**	Power (exponent)	Two	
10. Give the different bitwise operators.		
Operator symbol	Operation performed	Number of	
operands			
~	Bitwise negation	One	
&	Bitwise and	Two	
|	Bitwise or	Two	
^	Bitwise xor	Two	
^~ or ~^	Bitwise xnor	Two	
~&	Bitwise nand	Two	
~|	Bitwise nor	Two	

11. What are gate primitives?

Verilog supports basic logic gates as predefined primitives. Primitive logic function keyword provides the basics for structural modeling at gate level. These primitives are instantiated like modules except that they are predefined in verilog and do not need a module definition. The important operations are and, nand, or, xor, xnor, and buf(non-inverting drive buffer).

12.	Give the two blocks in behavioral modeling. 

1.	An initial block executes once in the simulation and is used to set up initial conditions and step-by-step data flow. 

2.	An always block executes in a loop and repeats during the simulation. 

13.	What are the types of conditional statements? 

1.	No else statement 

Syntax: if ([expression]) true – statement; 2. One else statement

Syntax: if ([expression]) true – statement; else false-statement;

3. Nested if-else-if

Syntax : if ( [expression1] ) true statement 1; else if ( [expression2] ) true-statement 2;

else if ( [expression3] ) true-statement 3; else default-statement;

The [expression] is evaluated. If it is true (1 or a non-zero value) true-statement is executed. If it is false (zero) or ambiguous (x), the false-statement is executed.

14. Name the types of ports in Verilog		
Types of port	Keyword	
Input port	Input	
Output port	Output	
Bidirectional port	inout	

15.	What are the types of procedural assignments? 

1.	Blocking assignment 

2.	Non-blocking assignment